Indoor communications of any digital data, whether it is high-speed signals carrying multiple HDTV programs or low-speed signals used for timing purposes, will be shared over a digital wireless network in the near future. Such indoor and home networking requires high data rates, very low cost and very low power consumption. Ultra Wide-band (UWB) system has enormous bandwidth to provide a promising solution to satisfying these requirements and becomes an attractive candidate for future wireless indoor networks. In such systems, synchronization plays very critical role to ensure correct and reliable system operation. Improper synchronization can introduce timing errors during transmission that can be eliminated using a device called scrambler. Simulation and implementation of data scrambler for UWB communication systems is discussed in the present paper. Model of the scrambler is build using Matlab to perform simulation. For FPGA (Field Programmable Gate Array) based implementation of UWB scrambler, Xilinx’s System Generator for DSP (Digital Signal Processing) tool is used along with Xilinx’s ISE Design Suite. Implementation and simulation results are then compared.